The present invention relates to improvement of a layout parameter extraction device for specifying and extracting a part of a circuit including parasitic elements such as a resistance and a capacity of an interconnect which are extracted from layout data when outputting the same circuit as a netlist in design of a semiconductor circuit.
In recent years, it has been important to recognize an interconnect from layout data, to extract parasitic elements such as a resistance and a capacity of the interconnect, to estimate values with high precision, and to simulate a delay time of a signal or the like in a circuit obtained from the layout data with high precision in a finer semiconductor process.
Procedure for obtaining a circuit including parasitic elements from layout data will be described below. First of all, an interconnect or an element such as a MOS transistor is recognized from the layout data to extract circuit information. In order to extract a parasitic resistance for each interconnect, then, the interconnect is divided in accordance with a shape of a circuit such as branch points or lengths, and nodes are generated on dividing points and node names are respectively assigned to the generated nodes. Thereafter, the parasitic elements such as a resistance and a capacity are extracted according to a predetermined interconnect model for each divided interconnect, and each terminal of the parasitic elements is connected to a proper node. Subsequently, a whole circuit is restructured to output a netlist of the circuit including the parasitic elements.
In the prior art, however, the case where a part of the circuit including the parasitic elements is specified to simulate the partial circuit has the following problems. Respective names are attached to identify each node generated on the dividing points of the interconnect and the like. In the name attachment, a layout parameter extraction device assigns the node names not so appropriately. For this reason, even if the node names are included in the netlist, it is difficult to recognize respective positions of the nodes in the circuit before extracting the parasitic elements. Accordingly, when simulating the partial circuit, it is hard to recognize, on the netlist, probing points for specifying the partial circuit.
In the case where the layout data has a hierarchical structure including an upper hierarchy and a lower hierarchy, it is impossible to recognize the names of the nodes generated on connecting points between the upper hierarchy and the lower hierarchy even if only the upper hierarchy should be extracted in order to shorten a time for extracting the parasitic elements. Similarly to the foregoing, when simulating the partial circuit, it is hard to recognize necessary probing points on the netlist.
Furthermore, the parasitic elements are extracted from a part of a large scale circuit. In the case where layout data of the large scale circuit has the hierarchical structure including an upper hierarchy and a lower hierarchy, it is necessary to specify nets belonging to the lower hierarchy as well as nets belonging to the upper hierarchy if the upper hierarchy and the lower hierarchy included in the partial circuit are to be extracted when restricting the partial circuit from which the parasitic elements are to be extracted. A lot of internal nets for coupling a plurality of transistors belong to the lower hierarchy in a cell having predetermined functions of, for example, an AND gate or the like. It is difficult to specify all the internal nets, and it takes a long time to do the same.